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Sparse Tensor Accelerator Modeling Tutorial @ ISCA 2021 [Part 1] (7/7)
dMazeRunner: Optimization Infrastructure for Programmable Dataflow Accelerators for Deep Learning
Dataflow-Architecture Co-Design for 2.5D DNN Accelerators using Wireless Network-on-Package
[FPGA'22] HeteroFlow: An Accelerator Programming Model with Decoupled Data Placement for FPGAs
Heterogeneous Dataflow Accelerators for Multi-DNN Workloads
ASPLOS'23 - Session 8B - Sigma: Compiling Einstein Summations to Locality-Aware Dataflow
Guest lecture: Hardware Accelerator for DNN part 1
Procrustes: A Dataflow and Accelerator for Sparse Deep Neural Network Training
Dataflow Hardware Acceleration of DNNs with High-Level Synthesis | Guest Lecture at Yale University
Timeloop: A Systematic Approach to DNN Accelerator Evaluation #accelerator #deeplearning
A flexible dataflow CNN accelerator on FPGA
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Last Updated: August 15, 2026
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![Full [CGO '22] Session 4 - Comprehensive Accelerator-Dataflow Co-Design Optimization for Convolutional Ne News](https://i.ytimg.com/vi/RKBuXUPhOcA/mqdefault.jpg)
![Sparse Tensor Accelerator Modeling Tutorial @ ISCA 2021 [Part 1] (7/7)](https://i.ytimg.com/vi/AXAuPfgiYaE/mqdefault.jpg)
![[FPGA'22] HeteroFlow: An Accelerator Programming Model with Decoupled Data Placement for FPGAs](https://i.ytimg.com/vi/PQ15-OGVttk/mqdefault.jpg)
