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An Efficient Accelerator for Deep Learning-based Point Cloud Registration on FPGAs (15min)
Design for Highly Flexible and Energy-Efficient Deep Neural Network Accelerators [Yu-Hsin Chen]
Dataflow Hardware Acceleration of DNNs with High-Level Synthesis | Guest Lecture at Yale University
All about AI Accelerators: GPU, TPU, Dataflow, Near-Memory, Optical, Neuromorphic & more (w/ Author)
Inside AI Infrastructure: How Data Flows from Archive to Accelerator
EnGN: A High-Throughput and Energy-Efficient Accelerator for Large Graph Neural Networks Chinese
[yarch23] #16 LoopTree: Enabling Exploration of Fused-layer Dataflow Accelerators
Procrustes: A Dataflow and Accelerator for Sparse Deep Neural Network Training
A High-Throughput FPGA Accelerator for Lightweight CNNs With Balanced Dataflow - ArXiv:2
The Fabric Architecture: Spatial Dataflow Computing Explained | Efficient Computer
A High-Throughput FPGA Accelerator for Lightweight CNNs With Balanced Dataflow - ArXiv:2
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Last Updated: August 17, 2026
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![Design for Highly Flexible and Energy-Efficient Deep Neural Network Accelerators [Yu-Hsin Chen]](https://i.ytimg.com/vi/brhOo-_7NS4/mqdefault.jpg)
![[yarch23] #16 LoopTree: Enabling Exploration of Fused-layer Dataflow Accelerators](https://i.ytimg.com/vi/AxDJK-urVnE/mqdefault.jpg)
