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Impact of FPGA Architecture on Resource Sharing in High-Level Synthesis
Dataflow Hardware Acceleration of DNNs with High-Level Synthesis | Guest Lecture at Yale University
Dataflow Accelerators for DNNs using High-Level Synthesis | Guest Lecture at Georgia Tech
High Level Synthesis (HLS) Explanation 11: Introduction to Finding Pipelined Schedules
FLOSS Tools for High Level Synthesis Integrating the FPGA into the Operating System
Video 3: Optimizing Power, Performance and Area with High-Level Synthesis (HLS)
SRC Formally Verified High Level Synthesis
Functional interfaces in higher-level synthesis
HPVM: Extending LLVM For Compiling to Heterogeneous Parallel Systems
High-level Data-Centric Parallel Programming for high performance BLAS on FPGAs - Xilinx XOHW20 161
SORS/WomenInBSC: Open-Source High-Level Synthesis Research for Automated FPGA/ASIC Acceleration
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Last Updated: August 17, 2026
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