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CFU Playground: Model-specific Acceleration on FPGAs - Timothy Callahan & Alan V. Green, Google
A RISC-V CPU on an FPGA, Built Entirely by Claude Code - Icepi Zero + Silice Fire-V, No Code Typed
Linus Torvalds: RISC-V Repeating the Mistakes of Its Predecessors
Building a RISC-V CPU from scratch.
Optimizing RISCV FPGA by caching spi flash in sram and a new open source soft core!
Introduction to FPGA Part 11 - RISC-V Softcore Processor | Digi-Key Electronics
MeganWachs - Keynote RISC-V and FPGAs: Open Source Hardware Hacking
RISC-V FPGA-based CPU and Language
Development of a RISC-V Based SoC Architecture using Open Source Tools for FPGA Technology
FeNN DMA A RISC V SoC for SNN Acceleration on FPGA
MeganWachs - Keynote RISC-V and FPGAs: Open Source Hardware Hacking
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Last Updated: August 17, 2026
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