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The RISC-V Vector Cryptography Extensions - G. Richard Newell & Ken Dockser
The Magic of RISC-V Vector Processing
RISC-V VSI-EA: Evaluation of Vector & SIMD ISA Instructions for embedded applications -BTU & Codasip
Easy vector optimisation with RISC V Vectors, Rémi Denis Courmont | FOSSASIA Summit 2024
The Real Challenge for RISC-V Vector Processors - John Min, Andes Technology
RISC-V Summit 2019: 78 RISC V Bit Manipulation ISA Extension Spec, Hardware, Software
Next-Generation Vector Processor Design III
SiFive Vector AI Processors Accelerated by the RISC-V Vector ISA by Vadim Malenboim, SiFive
RISC-V Vector Sail Model and Test Generation - Yifei Zhu & Xi Wang, RIOS Lab & Tsinghua University
Lightning Talk: Software Development for ML and RISC-V Vector Acceler... Lee Moore & Simon Davidmann
2019 EuroLLVM Developers’ Meeting: R. Kruppe & R. Espasa “Adventures with RISC-V Vectors and LLVM”
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Last Updated: August 17, 2026
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