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Software-defined Design Space Exploration for an Efficient DNN Accelerator Architecture
Challenges in Acceleration of Transformers on Dataflow Architecture | Mark Grobman
Dataflow-Architecture Co-Design for 2.5D DNN Accelerators using Wireless Network-on-Package
[FPGA'22] HeteroFlow: An Accelerator Programming Model with Decoupled Data Placement for FPGAs
Deep Learning Dataflow Accelerators
Understanding Reuse, Performance, and Hardware Cost of DNN Dataflows: A Data-Centric Approach
Heterogeneous Dataflow Accelerators for Multi-DNN Workloads
A flexible dataflow CNN accelerator on FPGA
Procrustes: A Dataflow and Accelerator for Sparse Deep Neural Network Training
FlexFlow: A Flexible Data๏ฌow Accelerator Architecture for Convolutional Neural Networks
[CGO '22] Session 4 - Comprehensive Accelerator-Dataflow Co-Design Optimization for Convolutional Ne
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Last Updated: August 16, 2026
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![[FPGA'22] HeteroFlow: An Accelerator Programming Model with Decoupled Data Placement for FPGAs](https://i.ytimg.com/vi/PQ15-OGVttk/mqdefault.jpg)
![[CGO '22] Session 4 - Comprehensive Accelerator-Dataflow Co-Design Optimization for Convolutional Ne](https://i.ytimg.com/vi/RKBuXUPhOcA/mqdefault.jpg)
