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RISC-V Summit 2019: 78 RISC V Bit Manipulation ISA Extension Spec, Hardware, Software
RISC-V Vector Performance Analysis
The Magic of RISC-V Vector Processing
The RISC-V Vector Cryptography Extensions - G. Richard Newell & Ken Dockser
Easy vector optimisation with RISC V Vectors, Rémi Denis Courmont | FOSSASIA Summit 2024
Implementation of an Out-of-order RISC-V Vector Unit- Roger Espasa, SemiDynamics Technology Services
RISC-V VSI-EA: Evaluation of Vector & SIMD ISA Instructions for embedded applications -BTU & Codasip
Vitruvius: An Area-Efficient RISC-V Decoupled Vector Ac... Francesco Minervini & Oscar Palomar Perez
Digital Design and Comp. Arch. - Lecture 19: SIMD Architectures (Vector and Array Processors) (S23)
Lightning Talk: Software Development for ML and RISC-V Vector Acceler... Lee Moore & Simon Davidmann
The Real Challenge for RISC-V Vector Processors - John Min, Andes Technology
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Last Updated: August 13, 2026
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